RISC-V Foundation Announces Initial Keynote Speakers for Inaugural RISC-V Summit

The RISC-V Foundation, a nonprofit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the keynotes for the first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018.

The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V community for a multi-track conference featuring tutorials, exhibitions and networking receptions. Leading technology companies and research institutions will share notable product updates, projects and implementations that accelerate the RISC-V ecosystem and reveal the future path for RISC-V. The initial keynotes for the Summit will be conducted by Antmicro, Facebook, Microchip, NXP, SiFive and Western Digital.

• Michael Gielda, Vice President Business Development of Antmicro: “Accelerating Innovation: Why Google's TPU Was Just the Start”
• Robert Shearer, Director of Silicon Architecture and Modeling of Facebook: “The 100X Problem – How to Redefine Silicon for Augmented Reality”
• Patrick Johnson, Vice President, Mixed Signal and FPGA Business Units of Microchip: “Enabling the Freedom to Innovate”
• Rob Oshana, Vice President, Software Engineering of NXP: “Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption”
• Yunsup Lee, Chief Technology Officer of SiFive: “Opportunities and Challenges of Building Silicon in the Cloud”
• Martin Fink, Executive Vice President and Chief Technology Officer of Western Digital: “Unleashing Innovation from Core to Edge”

“This year has been a hallmark one for the RISC-V Foundation,” said Rick O’Connor, executive director of the RISC-V Foundation. “The RISC-V ecosystem is continuing to grow at a rapid pace, surpassing 150 member companies from 25 countries across the world. We’re excited to bring the RISC-V community together at the inaugural RISC-V Summit and end the year continuing the momentum from all the RISC-V milestones that have been achieved thus far.”

Promotional pricing for the three-day Conference and Exhibition Pass is available for one more week, until Monday, Sept. 17. Register here to save $750 USD today. Student rates and group discounts of up to 35 percent are also available. To learn more about the packages and limited-time discounts, click here.

Sponsorship packages, media partnerships and exhibition packages are also available, see details here.

For press interested in attending, please email: risc-v@racepointglobal.com to receive a complimentary pass.

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

Contacts

Racepoint Global for RISC-V Foundation
Allison DeLeo, +1-415-694-6700
risc-v@racepointglobal.com

Original press release.